1. Field of the Invention
The present invention relates to a liquid crystal display device provided with a plurality of data drivers.
2. Description of the Related Art
There is described a liquid crystal display device in Japanese Patent Application Laid-open No. 11-194748 wherein a plurality of data drivers are connected in series by transmission lines to transmit display data and a data transfer clock. Each data driver is also provided with a buffer circuit between the transmission lines on either of the input and output sides.
The above related art, however, does not consider a change in duty ratio of transmitted pulse that may arise when a pulse transmission is performed. For example, in the case that the response characteristic of each buffer circuit is duller at a rise of a transmitted pulse than that at a fall thereof, the rise of the transmitted signal is delayed every time when it passes through a buffer circuit. This brings about a reduction of the transmission quality because the pulse width is decreased.
Even if the logic level of the transmitted signal (display data and a data transfer clock) is inverted every time when it passes through the buffer circuit on the output side of a data driver, a difference in duty once produced can not be canceled. For example, when the duty is 50% at the first data driver and 45% at the third data driver, it is expected to be about 40% at the fifth data driver. To say the least, it is not expected that the duty return to 50% again.
Further, in dual edge transfer wherein display data is taken in at rise/fall of a transfer clock, the margin of either of setup/hold times for each rising edge of the transfer clock differs from that for each falling edge. More specifically, in dual edge drive, since the transfer clock and display data have the same maximum frequency, the same line width for the transfer clock and the display data is used in input/output buffers and transmission lines. The difference in either of the delay time upon rise and the delay time upon fall between the transfer clock and the display data can thereby be narrowed within each path from the output buffer of one data driver to the input buffer of the next data driver. On the other hand, the delay time upon rise differs from that upon fall. As a result, some problems may arise. For example, for each rising edge of the transfer clock, the margin of the hold time is small though the margin of the setup time is sufficient. Inversely, for each falling edge of the transfer clock, the margin of the setup time is small though the margin of the hold time is sufficient. Sufficient margins of the setup/hold times are required for either edge. Consequently, the margin of either of the setup/hold times becomes insufficient.
It is an object of the present invention to provide liquid crystal display devices wherein changes in transfer clock and display data are suppressed.
It is another object of the present invention to provide liquid crystal display devices wherein there are increased margins of setup/hold times for display data.
In the present invention, a transfer clock input to a data driver is reproduced such that the deviations between the duties of the display data and the transfer clock input to the data driver and the duties of the display data and the transfer clock output from the data driver become small, and a latch clock is generated. The display data input to the data driver is latched on the basis of the latch clock.
Besides, in the present invention, a latch clock is generated on the basis of a transfer clock so as to increase the margins of setup/hole times of display data input to a data driver. The display data is latched on the basis of the latch clock. Preferably, the latch clock is generated such that it rises earlier than the transfer clock by a period t, and falls later than the transfer clock by the period t.